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--Title: 
--Purpose:
--Author:
--Date Created:
--Date last modified: 10/09/2011
--References: Chu page 31, 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library work;
USE work.MemoryPackage.all;
USE work.ControlPackage.all;

entity MMU_TopLevel is
	GENERIC ( memSize 	 : integer := 8;--The size of each memory elements, in bits
				 addressBits : integer := 5);--The number bits in the address
				 
	PORT ( Clk : in std_logic;
			address : in std_logic_vector((addressBits-1) downto 0);--Memory Address
			data_in : in std_logic_vector ((memSize-1) downto 0);--data to save
			data_out : out std_logic_vector ((memSize-1) downto 0);--data being read
			req : in std_logic;--Device requesting memory access
			rnw : in std_logic;--Read NOT write
			ack : out std_logic--Acknoledge operation complete.
			);

end MMU_TopLevel;

architecture Behavioral of MMU_TopLevel is	

	signal writeSignal : std_logic;--Used to connect the write control btwn components.
	
begin

	mmu_ram: Memory 
		generic map (memSize => memSize, addressBits => addressBits)
		port map (Clk => Clk, address  => address, we  => writeSignal, data_i  => data_in, data_o  => data_out);
		
	mmu_crtl: mmu_control
		port map (Request => req, RW  => rnw, clk => Clk, WE => writeSignal, Acknowledge => ack);
		
end Behavioral;